1. Field of the Invention
This invention relates to lithographic processing of microelectronics products and, in particular, to a method and system for inspecting masks used to project patterns in photolithographic imaging.
2. Description of Related Art
In manufacturing integrated circuits, it is a goal to build a defect-free photomask with the desired patterns, which then are projected and exposed onto the resist layers on a wafer during lithographic processing to create the circuits. Inspecting the photomasks is becoming more difficult because the mask patterns are becoming smaller. A variety of resolution enhancement technologies such as sub-resolution assist features, optical proximity correction and phase shift mask approaches may be used, and each of these has inspection issues. While the wavelength of the energy source used in the exposure tool continues to decrease, the wavelength of the energy source used in the inspection tool is lagging behind. Currently, the industry typically uses inspection tools with a light wavelength of 365 nm to inspect masks intended for exposure tools employing a light wavelength of 193 nm.
Some believe that an ideal mask inspection would be done with the same wavelength of the energy or radiation used in the exposure tool, and using exactly the same diffraction orders as the stepper. The AIMS system, invented by IBM Corporation and commercially available from Zeiss, can perform such an actinic inspection. However, it would be desirable to be able to completely inspect a mask in less time than that taken by the AIMS system. For certain attenuated phase shift masks (PSM), the lack of actinic inspection presents problems. For example, a 193 nm attenuated PSM is fairly transparent at the 365 nm inspection wavelength, which reduces signal contrast and makes inspection problematic. U.S. Pat. No. 6,023,328 discloses a method of inspecting a photomask by magnifying the image on a test substrate to a size larger than that on the mask. However, this patent does not disclose or suggest the manner in which specific fields may be exposed or how to optimize the resist layer on the test substrate.